Pulse discriminator and gate system



R. L. PHELAN PULSE DISCRIMINATOR AND GATE SYSTEM Oct. 8, 1963 2 Sheets-Sheefl l Filed Sept. l5, 1958 INVENTOR. ROY L. PHELAN AGENT R. L. PHELAN PULSE DISCRIMINATOR AND GATE SYSTEM oct. s, 1963 Filed Sept. 15, 195e 2 Sheets-Sheet 2 INVENTOR. ROY L. PHELAN AGENT United States Patent O 3,166,697 PULSE DISQRHMINATGR AND GATESYSTEM Roy L. Phelan, Plymouth, Mich., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Sept. 15, 19555, Ser. No. 761,171 2 Claims. (Cl. 340-168) This inventionpertains to means for improving the transformation of digits in decimal code to digits in a modified binary code.

More particularly, the invention relates to the magnetic writing circuit of an automatic accounting machine wherein information such as amounts, may be codally represented on a record medium which is inserted into the accounting machine. One of the purposes of the invention is to accurately translate decimal data contained in decimal switches into a modified binary code and place the information upon a magnetic track attached to a record medium. The invention contemplates the use of a circuit, in conjunction with the translating circuits, to accurately translate the data onto the magnetic strips or tracks of the record medium and make provision for the rejection of initial writing pulses which are not of the desired duration.

Certain portions of the invention are described but not claimed in a co-pending joint application of Deighton et al. Serial No. 598,454, tiled July 17, 1956, for Automatic Accounting Machine and assigned to the same assignee as the present invention. The present invention also contemplates the incorporation of a stepping switch into the circuit. Construction of the stepping switch is described and claimed in detail in a co-pending application i Deighton, `tiled March 4, 1955, Serial No. 492,247, now Patent Number 2,906,838, entitled Program Scanning Apparatus and also assigned to the same assignee as the present invention. The switch is designated SSS in the present application.

Therefore, it is an object of the invention to improve the transformation of data encoded in decimal form into data encoded in a modiiied binary code in an electronic computer.

It is another object of the invention to improve the accuracy of a circuit for encoding binary information and its complement upon a record medium.

It is a further object of the invention to provide a circuit having novel means for discriminating between a rst full pulse and a first partial pulse.

It is a still further object of the invention to provide a novel means incorporating the discriminating device of the invention which can also be used as a gate to inhibit the output of the discriminating device at a desired time.

In writing information magnetically on a document, two systems may be used, i,e, a synchronous system and an asynchronous system. In the synchronous system, the information is encoded upon the document when there is a coincidence of pulses between a timing generator and the information write circuit. lIn an asynchronous system, no timing generator is employed and there arises the problem of discrimination between a complete pulse and a partial pulse which may result due to the switching of the information pulse into the writing circuits after commencement of the pulse. This invention is capable of rejecting any initial partial pulses and encoding only the complete pulses on the magnetic record medium.

The magnetic record medium comprises a record having a plurality of different magnetizable areas thereon. For the purposes of this invention, there are at least two magnetizable areas or tracks upon which record data is or may be recorded. A rst magnetic track will be used to record the information data and a second magnetic area or track will be used to record the complement of the arrasar information data. The tirst area or track will be known i as the information or data track and the Second as the complement track.

lln .the present modified binary coding system, only two conditions of magnetization are utilized: ylvlagnetization of a discrete magnetic area in one polar direction is termed a one and magnetization in the opposite polar direction to the one is a zero, but since the code as an entirety is coded on two tracks rather than a single track, the zero direction of magnetization may also be considered an erase. In other Words the erase or zero is opposite of a one lf a one is to be written on the information or data track, it will be written on said track and a zero or erase ywill be continued on the complement track. Similarly, if

there is no information to be written on the information track, that track will continue to be erased and a one wiil be written on the complement track.

The aforementioned objects and other objects of the invention will become more apparent by reference to the ensuing description and the accompanying drawings in which:

FIG. 1 is a circuit diagram showing the incorporation of the invention into a magnetic writing circuit;

FIG. 2 is a circuit diagram showing another mode of accomplishing .the invention but capable of much higher speeds .than the magnetic writing circuit of FIGURE l.

Description of Invention Referring to FIG. 1 there is shown a pulse generator 21 having the contacts 1 and 2 and the cam 23. A constant voltage is applied to the contact 1. The output of the pulse generator is coupled through the conductor 25 to the contacts 13 and 10 of the WPG (write pulse gate) and the contact 16 of the RES (reset) contact. The WPG has the contacts 1S and 19 and also the contacts 10 and 11. As will be described later on, it is seen that the WPG also has the contacts 14 and 15. The RES has the contacts 16 and 17. The contact 19 of the NPG connects to the contact 1 of SSS-T1 (stepper switch 3-tier 1) through the conductor 33. Contact 11 of the WPG connects to the A contact of SSS-T2 through the conductor 35. The contact 1'7 of RES connects with the contact 1 of SSS-T3 through thelfconductor 37. SS3 is shown having three banks or tiers, each tier having an arm adapted to rotate and engage one of the four contacts of each tier. SSS is operated through the actuation or" the magnet coil 39.

The number three contact of SSS-T1 is connected to the contact 14 of the WPG, to the wiper arm of S82 through the conductor 41, and to the .grid 29 of the tube 31 by the conductor 27. The B contact of SSS-T2 `is connected to contacts 3, 4, and '5 of SS3-T3. The conductor continues from contact 5 of SSS-T3 through the winding of the magnet coil 39. Also connected to the 5 contact of SS3-T3 is a conductor to the lterminal 85;` At terminal 85, an inhibit voltage may be applied to inhibit the entry of pulses into the system which inhibition results in a gating action. A diode 98 is inserted before the terminal 85 to prevent the pulses to the magnet coil 39 from entering the scaling circuit 96. SSZ is actuated by the magnet coil 101 and its Wiper arm is used to energize the contacts of the decimal switches 43 'which have been set by some previous operation as described, for example, in the earlier mentioned Deighton et al. application S.N. 598,454. SSZ has l2. contacts (2-13) which communicate with 12 decimal switches in the box 43. With 12 switches, it is intuitively clear that a number of 12 orders may be stored in these switches. The decimal switches in the box 43 may have been set by the add racks or actuators of an accounting machine. Leading from the decimal switches box 43 are nine lines representing the decimal numbers l-9. rhese nine lines lead to the diode matrix 45 and are coupled to S81 through the conductors 47, 49, 51 and 53. S81 has a wiper arrn adapted to engage the contacts 2, 3, 4 and 5. 1e contacts Z, 3, t and are coupled respectively to the conductors 53, 51, i9 and 47.

S51 is stepped in response to the actuation of the mag-net coil 55 which is in series with B+, the resistor 57 and the tube 31. S81 will step four times for each one step of SSZ. SS1 is stepped each time a pulse is communicated to the tube 31 through the conductors 41 vand 27. Each time a pulse is communicated to the tube 311 causing this tube to conduct, the output of the tube is used not only to step S51 through its magnet coil 55 but also is used to actuate the scaling circuit 95 and step S52 once for every four steps of S81. Each time the tube 31 conducts, a pulse is received by the scaling circuit 95 over the conductor 97. The scaling circuit 95 is set so as to allow current to pass through the magnet coil 101 `once for every fourth pulse received by the tube grid 29. This pulse is of sufficient duration to step SSZ to its next contact. It is to -be noted that the switches SS1, S82 and S83 step only at the break of the pulse and not at the moment `of application of the pulse. Scaling circuits 95 Aand 96 are shown in block form as they are well known in the art and a showing :of their circuitry is not necessary for an understanding of the invention. For the understanding of the operation of a scaling circuit, reference may be made to Electronic and Radio Engineering, by

Frederick E. Terman, fourth edition (1955), pages 660 and 661.

rhe and `gate 59 has two inputs: the conductor 61 from the contact of the WPG and the conductor 63 from the inverter 39. The and gate 65 also has' two inputs: the conductor 87 from the wiper arm of SSI and the conductor 67 from contact 15 of the WPG. The inverter 89 is also coupled to the wiper arm of SSI. The output of the and gate 59 connects to the grid 69 of the ydual triode 71 and the `output of the and gate 65 connects to the grid 73 of this same tube 71. In circuit with the right-hand side of the tube 71 is the complement writing head 83 and in circuit with the left-hand side of the tube 71 is the data writing head 81. The function iof the and gate 65 is to pass a pulse and to cause the lefthand side of the tube 71 to conduct when information is to be Written on the information track of the record medium and not on the complement track and the function ofthe and gate 59 is to passa pulse Iand cause conduction tof the right hand side of the tube 711 when there is no information to be written `on the information track of the record medium but on the complement track. Both sides of the tube 71 cannot conduct at the same time as an output is present either at the output tof the an gates 59 or 65 and never both at the same time.

Description 0f Operation A write operation is the action of converting the amount stored in the decimal switches box 43 into a modified binary coded decimal representation and then encoding and storing this converted data magnetically on a magnetic tape or on the magnetic portion of a record medium.

To maintain the desired coding sequence, the highest order digit tand highest order bit, or twelfth digit position, the seven bit, is written first and so on progressively to a lower order so that the last bit to be written is the units position digit, the one bit.

For the purposes of this explanation, we will assume that 48 bits are to be written yon the complement and the data or information tracks but it is understood that the system can be expanded to write or encode any number of bits. Where, for example, there is no information data, such as the one, two and seven bits for a digit four, these three bits will be magnetically encoded on the complement track. The four or data bit Will be magnetically encoded on the information track. Similarly, if a six is to be written on the magnetic portion of the record medium, the two and the four bits will be written in the data or information track and the one and the seven bits will be written by the complement head on the complement track.

in the case of writing, referring more particularly to FlG. l, the data head S1 and the complement head 53 are shown as connected to individual plates of a dual triode write tube 71, which in the illustrated embodiment is shown to lbe a type 5687. The trio-de which is connected to the data or information head 81 is termed the information or data write tube and the triode which is connected to the complement head -83 is termed the complement write tube. The complement and data write circuits Iare shown schematically in the aforementioned figure.

When the write tube '71 is not conducting, the current flow through both magnetic heads will be from 250 volts through the plate resistor and through the magnetic head to volts. The magnetic tracks will thus be polarized in what is designated as a negative or Zero direction and any information on the track will be effectively erased. The magnetic polarity of any discrete areas will now be representative of :a Zerof When the tube is conducting, the current flow through the hea-d will be in the opposite direction. The circuit is from l150 volts through the magnetic head and through the tube 71 to ground. The magnetic track on the recond medium will then be polarized in what is designated as a positive direction or representative of a one and the selected information or data will be recorded on the tracks. It follows from the foregoing that new information can be written magnetically on the magnetizable portion of the record medium through the expedient of controlling the conduction of the data and complement write tubes.

As previously explained, if a one is to be encoded on the Idata track, the one is encoded on this track and an erase is continued on the complement track. Conversely, when a one is to be encoded on the complement track, the data track continues to be erased. 1n order to simplify the circuitry, both magnetic heads are continuously erasing (or encoding zeros) on their respective tracks and conduction of the proper side of the tube 71 will encode a one on the desired track by changing the direction of the current flow through the magnetic head.

As the record medium (not shown) is moved under the heads by a record moving means (not shown), the entire portion of the track on the record medium which is scanned by the magnetic heads will either be erased or have areas representative of ones, because there is a'lways a current flowing through the heads, in either the erase or write one direction.

The amount to be encoded on the magnetic track is set up and stored in the decimal switches box 43 and these switches may comprise a series of movable operating contacts having ten fixed contacts per switch, which are well-known in the art. The operating contacts for each digit are tied together. The ten fixed contacts of each digit are tied to a common line which represents a nine, an eight, a seven, and so on down to a one line. Only one operating Contact for each order will be closed and this will represent the digit stored.

The nine individual lines representing the numbers 9 to 1 are electrically -connected to the diode matrix l5 where the decimal information in the switches is converted into the modified binary Icoded decimal information. The output of the diode matrix 45 is as earlier mentioned, connected to SSI and consists of four electrical lines each representing a bit There is illustrated herein a seven bit tline, a four bit line, a two bit line and a one bit line. The decimal lines entering the diode matrix 45 from the decimal switches fait are electrically interconnected so as to form a combination of the bits J The nine line has two diodes connecting it to the seven bit and two bit lines, the eight line has two diodes connecting it to the seven bit and the one bit lines, the seven bit has a `single diode connecting it to the seven bit line, and so 011 down to the one line which is connected through a single diode to the one bit line. Diodes are used in the diode matrix 45 so that any decimal line having a voltage on it or which is electrically hot cannot make another decimal line hot inasmuch as the back resistance of the diodes makes all de-cimal lines into the bit positions unidirectional as far as current ilow is concerned.

The input to the decimal `switches 43 and the output of the diode matrix 45 are scanned by the wiper arms of their respective switches being actuated by the passage of current through their respective magnet coils SS and `101. As pointed out previously, SS2 steps once for each four steps of SSl. S82 is used for digit scanning while SSl is used for selection of the correct bit As in reading then, SS1 will step once for each possible bit of information or in the example earlier set forth herein, 48 times. S52 will take one step for each digit position or step 12 ti-mes. On every write pulse, S81 will be conditioned to ,step on the break of the pulse, and on the break of every fourth pulse both SSl and SSE will be conditioned to step. This enables SSll to selectively scan all four bit positions of a particular digit before S82 selects the next successive digit position.

SSS and its magnet coil 39 which cooperate as a conditional pulse transfer means, are utilized in the write operation as a iirst full pulse -discriminator and also as a gate. This compound function is employed because of the speed of the operation of the step switches. A time of l() milliseconds must be provided from the Ileading edge of one pulse to the leading edge of the next pulse. If this time were reduced, an error might occur. The magnet coi-l (not shown) which controls the make or break ofthe contacts 16, 13 and l14 of WPG (write pulse gate) is not synchronized with the action of the pulse generator 2d; therefore, it is possible that the Contact points of WPG could make at a time which allows a fraction of a write pulse to be transmitted to S83, the relay 4coil 39, the write tube and the scanninfy circuit. This pulse may not have a suicient time duration to step SSS but would be recorded on a magnetizable track of the record medium and would cause an erroneous number of pulses or digit to be recorded on the record medium. It the correct number of pulses were encoded upon the record medium because the first pulse was long enough to operate SSS, the leading edge of the first pulse received from the continuously operating pulse generator 21 would be less than l0 milliseconds from the next by that fraction of the `first pulse that was lost. lt is necessary, therefore, that the irst pulse to be recorded be a complete 3 millisecond pulse.

As before-mentioned, the construction and operation of SSS is descriibed and claimed in detail in the co-pending application of Deighton, Serial No. 492,247, now Patent 2,906,838. Briey, the `step switch in the copending application comprises a rocker arm which is energized by the step .switch coil 39. The energization of the coil 39 pulls a clapper into engagement with the rocker arm which locks the rotary contacts of the step switch so that the step switch does not move from its initial position but will remain on the same Contact. When the pulse is extinguished or breaks, the step switch coil through the clapper and rocker arm allows the `step switch to advance one step. The step switch is so constructed that a partial pulse, that is, a pulse of less than a predetermined length, is not sudicient to move the rocker arm and clapper and cannot, therefore, cause stepping of the .switch upon the break of the pulse. A partial pulse or a segment of a pulse which passes through the contacts 1t) and 11 of WPG, to the B Contact of SS3- tier 2 and thence through the magnet coil 39 to ground, would not be of suliicient duration to step SSE so the pulse passes on to ground and would not enter the write circuitry.

Therefore, it can be seen that the step switch performs the function of a rst full pulse disoriminator in that it is puise length responsive, rejecting all partial first pulses and stepping only when a full pulse is passed through the magnet coil 39. Herein, the term complete pulse indicates a pulse having the same length as that normally produced by the pulse generator. The term lfull pulse means a pulse of at least that predetermined length, i.e., time duration, which will activate the discriminator.

This same step switch is used as a gate by virtue of the utilization of an inhibit voltage to cause the switch to step from an active Contact to a contact preventing pulses from entering the writing circuits. In the example set forth herein, the .circuit is conditioned to write only 48 complete pulses at which time the scaling circuit 96, after receiving the 48 complete pulses from the conductor 41, presents an inhibit voltage at the terminal and steps the step switch SS` to prevent further pulses from entering the write circuit. The 48 pulses are counted by the scaling circuit 96 which, as noted, is designed toemit a pulse for each group of 48 pulses which it receives.

Thus, the stepping switch S53 and its associated magnet coil 39 have cooperated as a conditional pulse transfer means and acted as a irst full pulse discriminator and as a gate circuit.

rFhe first volt pulse from the pulse generator 21 generated by the engagement of contact 2, with contact 1 by means of the cam 23, will go through the WPG 18 and li) (assuming the relay coil of WPG, not shown, has already been energized but not the relay coil of RES, not shown) and be applied to the rotary contact of SSB-tier 1. Since the wiper arm is on the number 2 contact, this pulse iinds an open circuit. This emitter pulse also goes through WPG 16B and 11 and is applied to SS3-tier 2 through the rotary contact or Wiper arm, to the B contact and thence through the magnet coil 39 of S83, causing that relay coil 39 to be energized. As aforementioned, if this pulse is adequate to actuate the armature of SSS, i.e., a full pulse, S83 will step its rotary contacts from 2, B and 2 of the tiers i, 2 and 3, respectively, to contacts 3, C and 3 on the break of the pulse. `if the pulse is inadequate in time duration to actuate the armature and thus not step S83, the next full pulse will be applied across S53 magnet coil 39, through the same circuit, causing the step switch rotary contacts to step on the break of that pulse. The rotary contact of step switch S-tier 2 will step from E, to an open point, or contact C, thus breaking the circuit to the magnet coil 39. The rotary contact of SSB-tier 1 will step to `contact 3 which will allow the succeeding pulses to scan the decimal switches box 43 through the conductor `41 and SS?. for magnetically encoding the numbers contained in the decimal switches box 4?. Since the step switch requires approximately yfour milliseconds to step its contact from the break of one pulse to the make of the next Ipulse, and the time between pulses is seven milliseconds, the first pulse available to the write circuits through the step switch contact located at SSS-tier 1, contact 3, will always be a complete 3 millisecond pulse. The succeeding pulses emanating from the pulse generator 21 and traveling through SSS-tier 1, will be seen by the Write `circuits and the scanning circuits. The pulses cannot pass to contact 3 of SSE-T3 because the magnet coil of RES has not been activated as yet.

The succeeding pulse from the pulse generator 21 or the first pulse to be recorded, will travel through the contacts "i8 and 19 of WPG, through the rotary or wiper arm of SS3tier 1, to contact 3 and -will go to an input on the and gate '65 and the input on the and gate 59 through the contacts 14 land 15 of WPG. The and same as that :of FIGURE 1 in that the first pulse from the and gate 75 will be applied to the Wiper arm of S82, t0 the and gates 59 and 65, and to the tube Si over the conductors 27 and iii to step S51 by its magnet coil 55 to read the values stored in the decimal switches box 43.

The iirst pulse through the and gate 75 must always be a complete pulse since the iiip-iiop "F9 can only change state during the oft time of the earn contact 23 of the pulse generator Z1 because of the timing invoived. During the Writing operation, a relay coil, not shown, will open the contacts and 9 of WPGD so that the iiipdiop 79 cannot be turned on immediately after the insertion of the inhibit voltage to stop the writing on the record medium at the conclusion of the desired number ot pulses. T he circuitry has thus acted as a gate by resetting the flip-flop 79 at the conclusion of the desired number of pulses. The resetting 1of the iiip-fiop '79 conditions the and gate 75 off so that only the desired ntunber or" complete pulses are written.

The writing operation is concluded with the encoding of 12 digits in a inodied binary coded `form on the magnetic strips or tracks of the record medium. The circuitry has acted as a first vfull pulse discriminator by rejecting the initial pulses if they are not of sufficient time duration and as a gate by the application of an inhibit voltage to prevent the pulses from entering the Write circuitry at a specified time.

i claim:

l. ln a system utilizing complete pulses in dual outputs and receiving pulses through an asynchronous switch,

a device for rejecting initial pulses of less than a predetermined length and for gating a preselected number of complete pulses to said outputs comprising a iirst and gate, a direct connection between said asynchronous switch and one input of said first and gate, pulse length responsive means coupled between said switch and another input of said iirst and gate, having actuating means made operative only by the receipt thereto of a predetermined length of pulse and actuated no later than the cessation of the `first pulse of at least that predetermined length from said asynchronous switch, second and third and gates, the output of said iirst and gate being. coupled to one input of each of said second and third and gates, switching means coupled between another input of said second and gate and the output of said tirst and gate, electrical inverting means coupled between said other input to said second and gate and another input tosaid third and gate, and means coupled to said tirst and gate and to said pulse length responsive means to inhibit passage of puises through said rst and gate after the passage of a preselected number of pulses therethrough.

2. The combination as deined in claim 1 wherein said pulse lengtht responsive means comprises a flip-ilop triggered by a univibrator.

References Cited in the le of this patent UNiTED STATES PATENTS 2,403,873 Mumma Iuly 9', i946 2,545,464 Hoeppner et al Mar. 20. 1951 2,696,599 Holbrook et al. Dec. 7, 1954 2,810,122 Lanning Oct. 15, 1957 2,812,509 Phelps Nov. 5, 1957 2,912,672 Loper Nov. l0, 1959 FOREEGN PATENTS l 770,034 Great Britain Mar. 13, 1957 OTHER REFERENCES Aritlnnetic Operations in Bigital Computers, by R. K. Richards, pp. 78, 719, and 126, Van Nostrand Co., 1955.

allows the voltage to remain on the conductor S7 -Which communicates with the and gate 65. At this point, both inputs to the and gate 65 have a potential on them and consequently an output is obtained over the conductor 93 which communicates :with the grid 73 of the tube 71. Conduction of the left hand side of the tube 71 ensues and a magnetic polarization representative of a one is made upon ythe information or d-ata track of the record medium.

Similarly, the next pulse will find SSI on its number contact and as explained previously, this line is electrically hot and the subsequent conduction of the and gate 65 causes a magnetic polarization representative of a one to be placed upon the information track of the record medium.

This process continues until the whole number 038000017459 has been iwritten on the information and the complement tracks of the record medium.

At the conclusion of the 49th pulse, the iirst full puise being used to step S83 and the next 48 complete pulses -being encoded, an inhibit voltage is applied to the terminal 35. The scaling circuit 96 has connected the emitter pulse to terminal S5 las this device emits a pulse for every 48 Ipulses received. The pulse emitted is suflcient to step S83 through the action of the energization of the magnet coil 39 'associated with that stepping switch. Stepping SSS-T1 rotor from contact 3 to 4 will open the circuit to the emitter 21 thus preventing any further pulses 'from reaching the write circuits.

A relay coil associated with the contacts 16 and 17 of RES (the relay coil is not shown) will close the contacts 16 and i7 of RES upon energization and pulses will be applied from the pulse generator 2l through SS3- tier 3 until the rotor of tier 3y steps off the number 5 contact thus placing S83 in its -horne position.

The cycle is ready to be repeated as soon as a new amount is placed in the decimal switches box 43.

Thus, 48 complete pulses have been written on the record medium which is representative of the decimal number 038000017459. The S83 'and its associated relay coil 39 has functioned as a iirst full pulse discriminator in that it has rejected all initial pulses of insuliicient time length -to step S83. It has acted as a gate in 'that the S83 has stepped olf its active cont-acts upon the application of an inhibit voltage and thus precluded a voltage from -appearing yat either of the and gates 59 or 65 The speed of operation of the device of FIGURE l can be measurably increased by means of the circuit of FIGURE 2 which is similar to FIGURE l except that S83 and its associated relay coil 39 have been deleted 'and an electronic circuit comprising an and gate, a univibrator, la ip-flop and lesser circuitry has been substituted therefor and comprises conditional pulse transfer means.

Referring now more particularly to FGURE 2, there has been substituted lfor contacts 1.0 and il of WPG, contacts 16 and vi7 of RES, contacts 14 and l5 of WPG and S83 with its magnet coil 39, the electronic circuit comprising the and gate 75, the contacts 8 and 9 of WPGD (write pulse gate delay), the univibrator 77 and the flipflop 79 and the write relay point contacts 6 and 7. The remainder of the circuits of FEGURES 1 and 2 are substantially identical and will therefore, not be described again in detail.

The and gate 75 has two inputs: one from the contact 19 of WPG and the other from the output of the iiip-tiop 79. The univibrator 77 has an input from the contact 9 of WPGD and an output to the flip-flop '79. The ilipflop 79 has connected thereto a lead from a source of inhibit voltage which will place the flip-flop 79 in its oi condition. Also leading from the nip-flop is the contact 6 of the write relay point. The Contact 6 is adapted to engage the contact 7 of this relay when Writing begins to set the flip-fiop in its off position. If the flip-flop 79 is already in the off position when this contact makes, no change of state will occur. The univibrator' 77 and the first Hip-Hop 79 act as pulse length responsive actuating means to control gate 75.

The output off the and gate communicates with the stepper arm of S82, the grid of tube 31, and gate 65, the and gate 59, and the scaling circuit 96.

In FIGURE 2 of the electronic circuit, which has been substituted for S83 and its associated relay coil 39, is used to write the same number, ie., 038000017459, as before upon the complement and data tracks of the record medium. The dip-flop 79 is a conventional one having two stable states, i.e., a state where it is o and a state where a high output is applied to the and gate 75 over the `conductor 105. The univibrator '77 can be a 2-3 millisecond pulse duration responsive device capable of triggering the nip-flop.

When the information is to be written after the decimal switches box 43 have been set, a relay coil, not shown, will be actuated and close the contacts 18 and 19 of WPG as shown in dotted outline in FGU'RE 2. This will allow the pulses from the pulse generator 21 to enter the circuit. The first full pulse from the pulse generator 21 will not be written on the record medium but is used to condition the circuitry for writing. The first full pulse will be applied to the and gate 75 over the conductor E03 and also to the univibrator 77 through the normally closed contacts S and 9 of WPGD I(write pulse gate delay). The first full pulse is delayed in its path through the univibrator 77 and the flip-nop 79 long enough so that no coincidence 4of inputs appears at the input points or conductors and E05 of the and gate 75. Therefore, no output is derived from the and gate 75 during the application of the iirst full pulse to the conductor `103 and the univibrator 77.

The delay through the univibrator 77 and the flip-flop 79 is caused by the triggering of the flip-flop 79 from the trailing edge of the pulse output from the univibrator 7'7. rllhe univibrator 77 supplies a pulse having an operating time length measured between the leading and trailing edge thereof that is at least equal to the pulse duration time of the individual pulses of the pulse generating means 2l but less than the off time of the pulse generator 2l.

if the rst pulse is a full pulse, the univibrator is triggered into conduction, and the trailing edge of the output pulse from the univibrator is utilized to cause the Hip-flop 79 to change state. This causes the output of the ip-flop 79 over conductor 105 to. the and gate 75 to open the and gate Ifor the next pulse after the first full pulse, since the first full pulse has already terminated during the duration of the univibrator pulse.

lf the first pulse is not a full pulse, i.e., not of suflicient time duration to trigger the univibrator 7'7, the univibrator 77 remains non-conducting and the circuit awaits the arrival of the first full pulse. It is thus clearly evident from the foregoing that the circuit has acted as a first full pulse discriminator in that it is capable of rejecting a pulse which is not of suicient time duration to trigger the univibrator 77 and accurately place a magnetic mark upon the record medium.

Assuming the first pulse Was not of suiicient time duration to trigger the univibrator 77 and produce an output to the flip-dop 79, the second pulse, if full, will trigger the univibrator 77 and the trailing edge of the pulse from the univibrator will cause the flip-flop 79 to change state, and condition the output of the flip-flop 79 lover the conductor M5 at some potential dependent upon the circuit parameters ofthe Hip-flop 7 9.

With a voltage now appearing on the conductor 105, subsequent pulses applied to the univibrator 77 and to the and gate 75, will not affect the flip-Hop 79 but will cause the and gate 75 to emit an output pulse rfor each pulse from the pulse generator 21.

"llhe -circuit of FIGURE 2 now behaves substantially the 

1. IN A SYSTEM UTILIZING COMPLETE PULSES IN DUAL OUTPUTS AND RECEIVING PULSES THROUGH AN ASYNCHRONOUS SWITCH, A DEVICE FOR REJECTING INITIAL PULSES OF LESS THAN A PREDETERMINED LENGTH AND FOR GATING A PRESELECTED NUMBER OF COMPLETE PULSES TO SAID OUTPUTS COMPRISING A FIRST "AND" GATE, A DIRECT CONNECTION BETWEEN SAID ASYNCHRONOUS SWITCH AND ONE INPUT OF SAID FIRST "AND" GATE, PULSE LENGTH RESPONSIVE MEANS COUPLED BETWEEN SAID SWITCH AND ANOTHER INPUT OF SAID FIRST "AND" GATE, HAVING ACTUATING MEANS MADE OPERATIVE ONLY BY THE RECEIPT THERETO OF A PREDETERMINED LENGTH OF PULSE AND ACTUATED NO LATER THAN THE CESSATION OF THE FIRST PULSE OF AT LEAST THAT PREDETERMINED LENGTH FROM SAID ASYNCHRONOUS SWITCH, SECOND AND THIRD "AND" GATES, THE OUTPUT OF SAID FIRST "AND" GATE BEING COUPLED TO ONE INPUT OF EACH OF SAID SECOND AND THIRD "AND" 